One prior nonvolatile semiconductor memory is the flash electrically erasable programmable read-only memory ("flash"). Flash memories are programmed electrically and, once programmed, retain their data until erased. After erasure, flash memories may be programmed with new code or data.
Flash memories differ from conventional electrically erasable programmable read-only memories ("EEPROM") with respect to erasure. Conventional EEPROMs typically use a select transistor for individual byte erasure control. Flash memories, on the other hand, typically achieve much higher densities using single transistor cells. Some prior flash memories are erased by applying a high voltage to the sources of every memory cell in the memory array simultaneously. This results in the full array erasure.
Flash memory conventions define a logical one as a state where few, if any, electrons are stored on the floating gate of a memory cell. Convention also defines a logical zero as the state .where many electrons are stored on the floating gate of the memory cell. Erasure of the flash memory causes a logical one to be stored in each bit cell. Flash memory cells cannot be overwritten individually from a logical zero to a logical one without prior erasure. A flash memory cell can be overwritten individually from a logical one to a logical zero, however, because this entails simply adding the intrinsic number of electrons associated with the erased state to a floating gate.
The process for erasure, programming and verification of flash memories requires careful control of the voltages used to perform those steps. For example, one prior art flash memory is the 28F008 complimentary metal oxide semiconductor ("CMOS") flash memory sold by Intel Corporation of Santa Clara, Calif., which is an 8 megabit flash memory. Commands for reading, writing, and erasing are issued from a controlling microprocessor using standard microprocessor read and write timings. The flash memory includes a command register to manage electrical erasure and reprogramming. The command register contents serve as input to an internal state machine that controls reading, erasure and programming circuitry.
Address transition detection ("ATD") is also well known in the art and has been widely used in static read only memory (SRAM) and EPROMs. The purpose of address transition detection circuitry is to increase the speed with which data can be read from memory. This is accomplished by causing preparation circuitry to perform operations which are required for every memory read operation as soon as an address transition has been detected.
These operations include equalizing sense amplifiers and latching the previous output. The sense amplifiers are used to increase weak signals sensed from the memory cells to be read during the read operation. Equalizing the sense amplifiers causes the amplifiers to be cleared or otherwise set up so that they are ready to process the new data to be read. Latching the previous output causes the output to remain static until the new data from the read operation has been output from the sense amplifiers. The previous output is latched because the output of the sense amplifiers fluctuates before it finally reaches a steady value. Latching the previous output ensures that the swing does not pass down to the outputs.
Circuitry to equalize the sense amplifiers and latch previous output is well known in the art. In fact, both operations are normally performed during a memory read operation. The address detection circuitry simply permits these operations to be performed earlier than would be the case where address transition detection is not employed.
Noise on address lines, however, can cause an ATD scheme to fail. This is because there typically is a minimum amount of time required for the preparation circuitry (e.g. sense amplifiers and output latches) to reach a ready state where the read operation can be performed. If the noise causes a short duration ATD pulse that is shorter than the minimum time necessary for the preparation circuitry to stabilize, then the preparation circuitry will enter an unknown state and may cause unreliable data to be read.
One approach to handling address noise is to filter out any ATD pulses that are shorter than the minimum amount of time necessary for the preparation circuitry to reach a ready state. A method and circuitry for implementing this approach is set forth in co-pending patent application 07/901,276, filed Jun. 19, 1992. This filtering circuitry uses two delay chains. Each delay chain occupies precious area on the memory chip.